Here's the schematics of the Stereo Recorder:
Each nested chip is a Mono Recorder. Here's how a Mono Recorder is done:
It's actually a circle of OR gates. The "recording" is stored in the intermediate subnets.
Note that the above version is not binary-compatible with the original Stereo Recorder, that is, it does not produce the same savefile. The following version is binary-compatible, but it's a bit uglier:
The total chip length is 516 bytes, which exceeds two sectors by just 4 bytes. It's possible to reduce the length up to a point where four chips fit, more than doubling the total tape length.
The idea behind this is to use inverters instead of OR gates. The following section shows a design.
Here's a design using the above idea to build a 72-clock stereo recorder chip. It uses this nested chip as "tape":
That chip uses 190 bytes The master chip uses 4 instances of it:
The total size is 852 bytes, so there's still room for some more inverters in case a recording of more than 72 clocks is needed (remember the maximum is 1024 bytes). A mono recorder of about 150 clocks would also be possible.
When I was checking the design I noticed an anomaly which seems to be a bug. I don't know if that bug was removed in v1.1. It's in the input of one of the inverters in the nested chip:
It would probably be possible to make a "quad recorder", though the controlling logic would also take space. The idea is to have four pins for output, a recording input, an erase input and two "tape select" inputs that would make the recording and erasing pins act on the desired tape. I estimate that it can be done using eight extra ANDs and four inverters.
This is a TkGate diagram of the chip. It's somewhat complex. It has five nested chips, three of one kind and two of another. Both nested chip types are the same thing except for the pin layout, probably to avoid too many crossings. I've titled them LNC (Left Nested Chip) and RNC (Right Nested Chip).
This time I didn't take the effort to draw the junctions in RO-style. I have placed buffers because TkGate doesn't allow me to interconnect two module outputs. For the simulation I used the same flip-flop as in the Wall Hugger. In order for the simulation to work properly, I needed to adjust the inverter to a custom delay of 8 cycles.
Every nested chip is a bit in the chain. Let's examine just the LNC, as the RNC is the same with some pins different. But first, note that the inverter plus the AND gate make a raising edge detector that throws a 1-clock pulse every time the count pin is active.
Pin 7 is obviously the reset pin. When it is activated, the flipflop is reset.
Pin 6 is the Pulse input.
Pin 8 is the Previous Output input pin. When it is 1, it means that the previous output is set, so we're next. When that happens, the AND gate gives permission to the counting pulse to pass through and set the flipflop.
When the flipflop is set, it must be reset at the next counting pulse, so the output is fed back to the Reset input through an AND gate with the counting pulse.
Pin 5 is the Next Output pin for chaining. Pin 2 is for connecting to the main chip's pin.
Now for the main chip circuit. There are five chips to feed five outputs, plus two extra flip flops. The lower one in the diagram is initialized to 1 on reset, because it acts as the "previous output" for the first nested chip, so that it knows it's its turn. It is reset by the output of that first nested chip.
The upper flipflop is the last bit in the chain. That bit has a special treatment because it must not be reset on the next pulse, only on global reset.
Here's the TkGate version of the circuit for download:
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